Design for testability method at register transfer level
The testing of sequential circuit is more complex compared to combinational circuit because it needs a sequence of vectors to detect a fault. Its test cost increases with the complexity of the sequential circuit-under-test (CUT). Thus, design for testability (DFT) concept has been introduced to redu...
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis |
| Language: | English |
| Published: |
2016
|
| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/81731/1/NorlinaParamanPFKE2016.pdf |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|