Design for testability method at register transfer level
The testing of sequential circuit is more complex compared to combinational circuit because it needs a sequence of vectors to detect a fault. Its test cost increases with the complexity of the sequential circuit-under-test (CUT). Thus, design for testability (DFT) concept has been introduced to redu...
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| 格式: | Thesis |
| 语言: | English |
| 出版: |
2016
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| 主题: | |
| 在线阅读: | http://eprints.utm.my/id/eprint/81731/1/NorlinaParamanPFKE2016.pdf |
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