Register transfer level design of compression processor core using verilog hardware description language

Register transfer level design of compression processor core using verilog hardware description language

Throughput independent and parameterized data compression processor core was designed to tackle the needs of high-speed data compression applications. The design is based on combination of LZSS algorithm and Huffman coding, which enables it to be used in compression of a wide variety of data types....

وصف كامل

محفوظ في:

التفاصيل البيبلوغرافية
المؤلف الرئيسي:	Mohd. Sabri, Roslee
التنسيق:	أطروحة
اللغة:	English
منشور في:	2007
الموضوعات:	TK Electrical engineering Electronics Nuclear engineering
الوصول للمادة أونلاين:	http://eprints.utm.my/id/eprint/11398/1/RosleeMohdSabriMFKE2007.pdf
الوسوم:	إضافة وسم لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!

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